By phase aligning all the incoming signals with a local clock at the system synchronous frequency or bit rate, the signals can all be subsequently synchronously processed at receivers or repeaters using the same local clock. Such alignment also obviates the need to route a clock with each data channel or to use timing recovery circuits to recover the clock from the data streams.
Digital telecommunication networks are evolving at higher transmission rates, due in large part to the wide bandwidth made available by lightwave technology. Such networks are also evolving toward synchronous architectures of the type described above, with the identical synchronous clock frequencies available throughout the network. Furthermore, phase slippage between such bit synchronous channels becomes a greater problem with high bit rates, since a small change in propagation velocity, for example caused by the heating of an optical fiber, can result in phase slippage of up to several time slots.
The need for phase alignment exists not only in copper and optical fiber transmission systems but also within systems locally, for example, from bay to bay, shelf to shelf, or even from board to board, where the high bit rates can result in differental delays of a substantial portion of a time slot, or even multiple time slot delays, even with small path length differences. A digital phase aligner must be capable of correcting phase errors of several time slots. One source of delay variation is the temperature coefficient of propagation delay of optical fibers, which can be of the order of 30 picoseconds/km/.degree. C. Different temperature variations along different transmission paths can result in several time slots of phase excursion when the bit rate is of the order of 150 megabits/sec.
Prior art techniques of achieving phase alignment include the use of a FIFO (first in-first out) shift register and, a phase locked loop, arranged to recover the phase-varying clock frequency of the incoming data stream. The recovered clock is then used to clock the incoming data into the FIFO register and a local master clock is used to clock it out thereof. Each of the incoming channels employs such a FIFO and phase locked loop and each uses the same master clock. This circuitry requires more hardware than the present invention.
In my co-pending application entitled "Digital Phase Aligner", Ser. No. 946,323 filed Dec. 24, 1986, which issued on July 5, 1988 as U.S. Pat. No. 4,756,011, a first generation phase aligner, hereinafter referred to as DPA1, is disclosed and claimed. The differences between the DPA1 and the recent invention are explained in detail below.